Ruben Reyes
ASIC Physical Design • Timing/Power • ML/AI

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Principal ASIC Physical Design Engineer with 30+ years in RTL-to-GDSII delivery, timing closure (PrimeTime), power analysis (PrimePower/PT-PX), and low-power UPF across advanced nodes down to 4nm. Strong automation in Python/Tcl and practical ML/AI for EDA workflow optimization.